At high frequency transmission rates, when bits are transferred in parallel on the same bus, for example at the interface between a telecom chip and a network processor, a misalignment of the bits often occurs. This misalignment, commonly referred to as the “skew”, is often due to transmission path differences, but can also result from other factors such as impedance mismatches or delays in the clock signals. When bits are transferred in parallel at high speed, they go through different paths, and therefore have different arrival times.
FIG. 1 shows a telecommunication system 10 comprised of a source (emitter) 11 and a sink (receiver) 12 that exchanges bits via a network 13, typically a bus comprised of a plurality of transmission lines. This illustrates the skew that can occur on a set of bits transmitted in parallel vis a vis a clock signal. As shown in FIG. 1, the slight misalignment that can be noticed at the output of the source 11 is significantly increased after the network 13 before it is applied to the sink 12. To be able to retrieve the bits in a correct order, a deskewing/alignment mechanism must be implemented as shown in FIG. 2.
Referring to FIG. 2, a deskewing and alignment block 14 is placed inside the sink 13 in a front end position to achieve this result before the aligned bits are processed in the functional logic block 15 as is standard. As a result, in a telecom IC chip, the deskewing/alignment function is performed between the input/output terminals (I/O's) and the functional logic of the chip.
For example, the Frame Based ATM level 4 or the SPI4 phase 2 protocols recommended respectively by the ATM and OIF forums, state that deskewing is only mandatory if the transmission lines (or links) are running at more than 350 MHz, but not for the lower frequencies (the standard transmission range starts at 310 MHz). When the bits are received in accordance with these protocols, a training sequence is sent inband periodically. The 20-word training pattern consists of 10 repeated training control words followed by 10 repeated training data words, wherein the training data word “1111000000000000” is orthogonal to the training control word “0000111111111111”. It is applied to a 17 bit-width data bus, 1 control bit being associated to each set of 16 bits.
In this context, the role of the deskewing/alignment block 14 is to suppress the skew and properly realign the data and control bits on the main clock. To that end, it analyses the border between the training control words and the training data words to determine the delay which must be added to each transmission line of the data bus to realign the bits. This delay defined during the training period is then applied to inband data bits.
As illustrated in FIG. 3, which schematically shows the block diagram architecture of the deskewing and alignment block 14 of FIG. 2, the deskewing/alignment function is usually performed in two separate blocks: the deskewing block and the alignment block, respectively referenced 17 and 18. The received main clock signal tdclk, the 16 data bits tdat and the single control bit tctl are applied to the deskewing block 17 as inputs. Note that the data and control bits are applied via a bus having a width of 17 bits on each edge of the main clock (double edge clock).
In turn, the deskewing block 17 generates an internal reference clock signal (ref_clk), 2*16 data bits (bit_tdat) and 2*1 control bits (bit_tctl), that are sent to the alignment block 18. Said data and control bits are aligned with said reference clock but misaligned with respect to each other. Finally, the alignment block 18 processes these bits and generates 2*16 data bits (tdat_desk) and 2*1 control bits (tctl_desk) that are still aligned with said main clock and are now also aligned with each other.
After reset, the source continuously sends training patterns until enough valid parity values are received. Each control word and especially each training control word includes a parity field which is a diagonal interleaved parity computed on all the data which have been received after the previous control word. The parity values will not be correct until the deskewing is properly done.
It is therefore desirable to have a deskewing/alignment block combination which renders the functional logic block totally skew insensitive on the totality of said standard transmission range. It is also desirable to avoid the need of switching between two telecom systems or operating modes depending on whether the transmission frequency is lower or higher than 350 MHz. It is further desirable to have a deskewing/alignment block combination that performs an automatic discrimination between the data sequences and the training sequences that are periodically sent inband. Finally, it is still further desirable that there is no interaction between the deskewing/alignment block combination and the functional logic block.